1 I/Q Data
1.1 What is I/Q Data
I/Q data stands for In-phase and Quadrature. They refer to two sinusoids that have the same frequency and are 90 degrees out of phase. By convention, the I signal is a cosine waveform, and the Q signal is a sine waveform.
1.2 Properties of I/Q Data
An I/Q sample is a complex number . and are real values often stored as float32 or 8-bit. I and Q are two sinusoids of the same frequency but 90 degrees apart in phase. A file or stream of I/Q data is just a 1D (1 dimensional) array of complex samples, typically interleaved as I0, Q0, I1, Q1, … . For example, at 2 mega-samples per second (Msps), the Software-defined Radio (SDR) is able to output 2 million complex samples per second, which is 2 million I values and 2 million Q values per second.
2 Software-defined Radio (SDR)
2.1 What is a SDR
It is defined as a radio communication system that utilizes software for the modulation and demodulation of radio signals, allowing for reconfiguration and upgrade capabilities in real time to accommodate various radio protocols.
It can be tuned to a specific frequency and receive a specific type of radio transmission. In the SDR architecture, the software defines the radio frequency, bandwidth, modulation, error correction and power.
2.2 Components of a SDR
2.2.1 Analog Radio Frequency (RF) "front end"
Analog RF front end is the part that handles the radio waves. In this stage, all signals are continuous voltages.
2.2.1.1 Antenna Connector and Switch
The antenna is a conductive element (a metal conductor) that converts electromagnetic waves travelling through the air into small, rapidly oscillating analog voltage at its terminals, and vice versa for transmission. When RF hits the conductive element, it forces the electrons in the element to oscillate back and forth, creating alternating current (AC). This voltage is extremely small, in the range of microvolts to millivolts.
The antenna connects to the SDR board through an SMA (SubMiniature version A) connector, which is a standardized metal RF connector designed to carry high frequency signals with minimal signal loss. RF switches are placed at this interface to route the signal between different antenna ports, frequency bands, or between the receive and transmit paths depending on the operating mode.
2.2.1.1 Filters
Contains band-pass, low-pass, or high-pass filters that remove the out-of-band signals that are outside the band of interest. If these are not removed, they can enter the amplification and mixing stages, causing distortion, interference, or overloading of downstream components.
2.2.1.1 Low-Noise Amplifier (LNA)/RF Amplifiers
Signals arriving from the antenna are usually weak. We use the LNA to boost very weak signals from the antenna while introducing minimum possible additional noise. Later stages may use variable gain amplifiers (VGAs) to adjust level.
2.2.1.1 Attenuators
It is a component that intentionally reduces the strength of a signal by a controlled amount, measured in dB. This is used in the event when the input signal is too large, which might cause overloading, ensuring that the signals are within the safe operating regions.
2.2.2 Frequency Conversion
The main purpose of the frequency conversion is to move the RF signal from its original high carrier frequency down to a much lower frequency that can be practically digitized by an ADC. Frequency conversion solves this by shifting the signal of interest down to near 0 Hz (baseband), where the ADC can capture it accurately.
2.2.2.1 Local Oscillator (LO)
It is an internal signal generator that produces clean and stable sine waves at a specific, programmable frequency. This reference signal is what the incoming RF signal is mixed against to perform the frequency shift.
The LO frequency is set to match the center of the frequency band you want to receive. For example, if you want to receive a signal at 915MHz, the LO is programmed to produce a 915MHz sine wave. The LO signal is generated via 2 components, namely a Crystal Oscillator (or TCXO - Temperature Compensated Crystal Oscillator) and a PLL (Phase-Locked Loop).
The crystal is a piece of quartz that mechanically vibrates at a precise and stable frequency (determined by its physical dimensions) when a voltage is applied. A TCXO has an extra compensation circuitry that corrects for small frequency shifts caused by temperature changes in the hardware, ensuring higher frequency accuracy over varying operating conditions.
A PLL synthesizer takes the fixed frequency from the crystal and multiplies it to generate the exact LO frequency required. PLL contains a feedback loop. Up till this stage, signals are all still voltages.
2.2.2.2 Mixers
A mixer is a circuit that multiplies two input signals together. When two sine waves at different frequencies are multiplied, the result contains two new frequency components: one at the sum of the two input frequencies, and one at the difference of the two input frequencies.
In a receive chain, the mixer takes the RF signal from the antenna path and the LO sine wave as its two inputs. The sum frequency is very high and is removed by a low-pass filter immediately after. The difference frequency is what is retained. It represents the original RF signal shifted down to a much lower frequency, close to 0 Hz (baseband).
To produce both I and Q components simultaneously, the SDR uses two mixers operating in parallel on the same incoming RF signal.
2.2.3 Baseband Analog Processing
After the mixers perform frequency conversion, the I and Q signals are at a low frequency near 0Hz. However, they are not clean or correctly levelled for the ADC. The baseband analog processing stage conditions these signals, before being digitized.
2.2.3.1 I and Q Branches
From the mixer stage onwards, the signal path splits into two parallel branches. One carrying the I signal, and the other carrying the Q signal. Every component from this point to the ADC is duplicated. There is one filter and one amplifier chain for I, and a separate filter and amplifier chain for Q. Both branches must be kept as electrically identical as possible. Any difference in gain or phase between the I and Q branches introduces IQ imbalance, which causes errors in the amplitude and phase of the final complex samples.
2.2.3.2 Analog Baseband Filters
After the mixers, each branch passes through a low-pass filter. There are two things removed by the filters. First, it removes mixer products. We desire the difference frequency and not the sum frequency. Therefore, we use this low-pass filter to remove the sum frequency. Second, we remove out-of-channel signals, which are outside our desired channel bandwidth. Cutoff frequency here is typically programmable and is supposed to match our channel bandwidth selected in software.
2.2.3.3 Variable Gain Amplifiers (VGA)/AGC
After filtering, we must set the amplitudes of the I and Q signals to be at a level appropriate for the ADC. This is an amplifier whose gain is adjusted in real time via a digital control signal.
This adjustment can be automated by the AGC (Automatic Gain Control) system. The AGC monitors the power level of the incoming signal and sends gain correction commands to the VGA to maintain a target signal level at the ADC input.
2.2.4 Data Converters
The data converter stage is the boundary between the analog domain and the digital domain in the SDR. All signal processing before this point operates on continuous analog voltages. All signal processing after this point operates on discrete binary numbers.
2.2.4.1 Analog-to-Digital Converters (ADC)
The ADC samples the analog input voltage at regular time intervals and converts each measured voltage into a binary integer. SDR uses 2 ADCs, one for the I branch, the other for the Q branch.
There are two parameters that change how the ADC operates. The first parameter is the bit depth. It is the number of binary bits used to represent each sample. A 12-bit ADC can represent distinct voltage levels. Higher bit depth means finer resolution, lower quantization noise, and greater dynamic range. The next parameter is the sample rate. It is the number of samples taken per second, expressed in Msps (mega-samples per second). This must be at least twice the signal bandwidth being captured, in accordance with the Nyquist sampling theorem.
2.2.4.2 Digital-to-Analog Converters (DAC)
The DAC performs the reverse operation. It accepts a stream of binary integer values from the digital front end and converts each value into a corresponding continuous analog output voltage.
2.2.5 Digital Front End
The digital front end is the programmable digital processing layer inside the SDR hardware that sits between the ADC/DAC and the host interface. It operates entirely on digital IQ sample streams and performs high-speed processing tasks that must happen on the SDR board itself, before data is transferred to the host PC.
2.2.5.1 FPGA/DSP
The core of the digital front end is an FPGA (Field-Programmable Gate Array) or a dedicated DSP (Digital Signal Processor). An FPGA is an integrated circuit that can be configured in hardware to implement any digital logic circuit. Unlike a CPU, which executes instructions sequentially, an FPGA executes many operations in true hardware parallelism simultaneously, making it capable of processing hundreds of millions of samples per second in real time.
In some SDR platforms, the FPGA, ADC, and DAC are all integrated into a single chip called an RFSoC (Radio Frequency System-on-Chip). In lower-cost consumer SDR dongles, the equivalent functions are split between a dedicated tuner chip and a USB controller chip.
2.2.5.2 Digital Down Converter (DDC)
The DDC is a processing block implemented inside the FPGA that performs frequency selection and sample rate reduction entirely in the digital domain. Even after the analog mixers bring the signal to baseband, the ADC may capture a wider bandwidth than the channel of interest. The DDC selects the specific sub-band of interest and reduces the data rate to match it.
The DDC performs three sequential operations:
- Digital mixing: A NCO (Numerically Controlled Oscillator) inside the FPGA generates a digital sine/cosine wave at a precise offset frequency. The incoming IQ samples are multiplied by this digital oscillator, shifting the target channel exactly to 0 Hz.
- Digital low-pass filtering: A digital filter (typically a CIC filter followed by FIR filters) removes all frequency content outside the desired channel bandwidth from the sample stream.
- Decimation: Once the bandwidth has been reduced by filtering, most of the samples contain redundant information. Decimation discards a fixed number of samples for every one that is kept. For example, decimation by 8 retains one sample for every 8 input samples, reducing the output sample rate proportionally. This dramatically lowers the data volume that needs to be transferred to the host.
On the transmit side, the equivalent process is called a DUC (Digital Up Converter), which performs interpolation (the inverse of decimation) and digital upconversion before the DAC.
2.2.5.3 Packet and Buffer Formatter
The DDC outputs a continuous, uninterrupted stream of IQ samples. However, data cannot be transferred to the host PC as an infinite continuous stream. It must be organized into discrete, finite-sized blocks. The packet and buffer formatter chops the continuous IQ stream into fixed-size buffers (e.g., 8192 samples per buffer) and attaches metadata to each buffer before it is queued for transfer.
Metadata attached to each buffer typically includes a timestamp indicating the precise time at which the first sample in the buffer was captured, referenced to the SDR's internal clock. It also includes a sequence number so the host can detect if any buffers were dropped during transfer. Lastly, it includes channel identifiers in multi-channel SDR configurations.
On the host side, the UHD driver receives these buffers, verifies their integrity, and makes the IQ samples available to the application as ordered, timestamped blocks.
2.2.5.4 Control Interface (SPI)
The FPGA must communicate configuration commands to the analog RF components on the board (the tuner chip, LNA, PLL, VGA, and filters) to set parameters such as center frequency, gain levels, and filter bandwidth. This is done over a SPI (Serial Peripheral Interface) bus.
SPI is a simple four-wire serial protocol used for low-speed control communication between a master (the FPGA) and peripheral chips (the RF components). It is entirely separate from the high-speed IQ data path. When the host software issues a command such as "set center frequency to 915 MHz", the UHD driver sends that command over USB to the FPGA, which then translates it into SPI transactions directed at the appropriate RF chip.
2.2.6 Host Interface, Power, Timing
This section covers the infrastructure components that connect the SDR board to the host computer, supply electrical power to all on-board circuits, and maintain precise timing synchronization across the entire system.
2.2.5.1 Host I/O Interface
The host I/O interface is the physical connection between the SDR hardware and the host PC. It carries two logically separate types of traffic over the same physical cable:
- Data traffic: the high-speed, continuous stream of buffered IQ sample packets from the FPGA to the host PC (receive direction), and the stream of IQ samples from the host PC to the FPGA (transmit direction).
- Control traffic: low-speed command and status messages between the host driver (e.g., UHD) and the FPGA, used to set operating parameters such as frequency, gain, sample rate, and streaming state.
The most common interface types used in SDR hardware are:
- USB 3.0: used in devices such as the USRP B205mini; provides up to approximately 400 MB/s of throughput.
- Gigabit Ethernet (1 GbE / 10 GbE): used in higher-end USRP N-series and X-series devices; provides deterministic latency and supports longer cable runs.
- PCIe: used in embedded and high-throughput SDR platforms for maximum bandwidth.
2.2.5.2 Power Supply and Voltage Regulators
The on-board circuits require multiple different supply voltages, each with specific noise and stability requirements. A single input source (such as USB 5 V or an external DC jack) is converted into the required rails by a set of voltage regulators.
Typical voltage rails on an SDR board include:
- 3.3 V analog supply: for RF circuits including the LNA, mixer, and VGA, which require a low-noise analog supply to avoid introducing noise into the signal chain.
- 1.8 V / 1.0 V digital supply: for the FPGA core logic and digital circuits.
- ADC/DAC reference supply: a highly isolated, low-noise supply dedicated to the data converters, as any noise on this rail directly appears as noise in the digitized IQ samples.
The analog and digital supply rails are physically separated on the PCB to prevent high-frequency switching noise from the digital circuits from coupling into the sensitive analog RF circuitry.
2.2.5.3 Clock and Timing
All components in the SDR that process samples (the ADC, DAC, FPGA, and LO PLL) must operate from the same clock reference. If different components use slightly different clock rates, samples become misaligned over time, causing phase errors and timing drift in the IQ data.
The clock and timing system provides this common reference:
- A crystal oscillator or TCXO on the board generates a stable master reference frequency (e.g., 40 MHz). All other clocks on the board are derived from this single source.
- A clock distribution circuit fans the reference signal out simultaneously to the ADC, DAC, FPGA, and LO PLL, ensuring all components are locked to the same timing base.
- High-end SDR platforms (including the USRP B205mini) support an external 10 MHz reference input, allowing the SDR to lock its entire clock tree to an external frequency reference such as a GPS-disciplined oscillator (GPSDO). This enables extremely high frequency accuracy and allows multiple SDR units to operate coherently as a synchronized system.